DB25 Bus Protocol and Port Map

The DB25 cable between the ISA card and the I/O board carries an 8-bit bidirectional data bus, an 8-bit host-to-board address bus, a data-direction line, and eight grounds. The cable itself is a standard female-to-female DB25 parallel cable.

There are no discrete read or write strobe wires. Read and write cycles are encoded as address ranges. The ISA card translates the PC's /IOR and /IOW into distinct high-address-bit patterns; the board's two 74LS138 decoders turn those patterns into buffer enables and latch clocks. The schematic annotates one decoder as covering 0b01_x000–0b01_x111 and the other 0b10_x000–0b10_x111.

All signals are 5 V and active-low. The bus is fully static: any cycle length from microseconds to seconds works, which allows cycles to be stretched for multimeter observation.

DB25 pinout

Measured by continuity and in pin-for-pin agreement with J1 on the IKA Victor schematic.

A6 is left unconnected on the board; the schematic states this explicitly.

Signal naming

The bridge sketch and earlier revisions of this documentation name signals after their observed behaviour rather than their schematic identity. The two naming schemes map as follows.

Cycle timing

Write. Set A0–A2 and the data lines. Assert select and /WREN low. Pulse the write-range bit low, then high — the output latches capture on the rising edge. Release select and /WREN.

The read-range bit must stay high for the whole cycle. Asserting it during a write switches an input buffer onto the data bus, which causes the latches to capture the current button states instead of the intended value; the visible symptom is lamps mirroring the buttons.

Read. Set A0–A2. Assert select and the read-range bit low. Sample D0–D7. Release.

Host port map

Ports are at base 0x100. Inputs are active-low: a released switch reads 1.

Read ports

Bits marked — are unassigned and read high. Ports 0x103, 0x104 and 0x105 are served by the on-board AT89C51 through its port chip-selects rather than by input buffers.

Port 0x105

This port was not documented in prior community sources. It was found by logging all ports for changes, and the schematic confirms it as an MCU-served chip-select.

Disassembly of the MCU firmware shows it carries an 8-bit coin counter that increments once per debounced coin, wrapping at 255 — not a switch level or a fixed-width pulse. See original-firmware.md.

Read the whole byte and treat any change in value as one credit. Detecting an edge on bit 0 alone registers one credit per two coins. The bridge sketch currently does the latter; this is recorded as a known issue in the top-level README, pending confirmation on hardware.

Write ports

Write ports 0x100–0x103 correspond to the four 74HC273 output latches driving the ULN2803A lamp sinks.

Bit assignments within 0x100 vary between cabinets. Many machines were rewired in service, particularly around the relay board. On the cabinet used for this work the assignment is:

Verify port 0x100 on your own machine with a chase test before relying on these. The schematic places COIN_CNTR among the low bits of this port on stock wiring.

This page is synced from docs/bus-protocol.md in the ez2-io repo.